This disclosure relates generally to semiconductor device fabrication, and more particularly to formation of interconnects in a semiconductor device using dummy gates.
Semiconductor devices may include both active gates, which are part of active devices such as field effect transistors (FETs), and dummy gates, which are not part of active devices. The dummy gates may be included in various locations in a semiconductor device for various reasons, for example, for across-chip line width variation (ACLV) improvement during device fabrication. In another example, active regions of a semiconductor device may be tucked underneath dummy gates to improve embedded silicon germanium (eSiGe) growth in source/drain regions of the semiconductor device. However, dummy gates may consume layout area in the semiconductor device, and while dummy gates may be helpful during device fabrication, they may not be useful in the final semiconductor device product. In addition, the presence of dummy gates may increase parasitic coupling in the semiconductor device, which may slow down switching signals between active devices.